Implementation of modified distributed canny edge detector algorithm using fpga

Edge can be defined as discontinuities in image intensity from one pixel to another. Edge detection is one of the most fundamental algorithms in digital image processing. Direct implementation of the canny algorithm has high latency and cannot be employed in real-time applications. To overcome these, an adaptive threshold selection algorithm is proposed. Distributed Canny Edge Detection using FPGA has high edge detection performance, but has high resource utilization. Here, to reduce the resource utilization we present modified distributed canny edge detection algorithm which uses approximate square root method. This algorithm divides the image into blocks and computes edges of the blocks in parallel. It is capable of removing excess edges in the image. Subjective test shows that performance of proposed algorithm is better than previous algorithm. Finally, it is implemented on Virtex-4 FPGA and synthesized using Xilinx ISE. The synthesized image uses 4 computation engines and obtains nearly 30% resource optimization in approximate calculation. To detect edges images from SIPI database are used.